1. Technical Field
The present invention relates to memory devices in general, and in particular to embedded dynamic random access memory devices. Still more particularly, the present invention relates to a method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices.
2. Description of the Prior Art
Embedded dynamic random access memory (DRAM) is a type of integrated circuit having both memory cells and their control circuits formed on a single semiconductor chip. Specifically, a complete embedded DRAM includes a transfer field effect transistor (FET), a capacitor coupled to the transfer FET, and a group of control circuitry. The transfer FET acts as a switch between the lower electrode of the capacitor and a bit line. Therefore, data within the capacitor can be written in or read out.
Embedded DRAMs are capable of transferring a large quantity of data at a very high speed. Because of their relatively high processing speed and storage capacity, embedded DRAMs have been commonly employed in various high-end integrated circuits, such as graphic processors. In addition, embedded DRAMs can provide a processor a faster access to larger capacities of memory at a lower cost than that currently available using conventional static random access memories (SRAMs) and/or electrically erasable programmable read only memories (EEPROMs).
The present disclosure provides a method and apparatus for concurrently communicating with multiple embedded DRAM devices by a processor.
In accordance with a preferred embodiment of the present invention, a data processing system includes a processor and multiple memory devices coupled to the processor. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There w are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block. The receiver that had received the occurrence of a cycle adjustment informs the other receivers that did not receive the occurrence of a cycle adjustment to use their cycle delay block to delay the incoming data for at least one cycle.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.